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M25P32-VMP6TP Datenblatt(PDF) 25 Page - Numonyx B.V

Teilenummer M25P32-VMP6TP
Bauteilbeschribung  32-Mbit, low voltage, serial Flash memory with 75 MHz SPI bus interface
PDF  53 Pages
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Hersteller  NUMONYX [Numonyx B.V]
Direct Link  http://www.numonyx.com
Logo NUMONYX - Numonyx B.V

M25P32-VMP6TP Datenblatt(HTML) 25 Page - Numonyx B.V

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M25P32
Instructions
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6.4.4
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W/VPP) signal. The Status Register Write Disable (SRWD) bit and Write Protect
(W/VPP) signal allow the device to be put in the Hardware Protected mode (when the Status
Register Write Disable (SRWD) bit is set to 1, and Write Protect (W/VPP) is driven Low). In
this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become
read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for
execution.
Figure 11.
Read Status Register (RDSR) instruction sequence and data-out
sequence
C
D
S
2
1
3456789 10 11 12 13 14 15
Instruction
0
AI02031E
Q
7
6543210
Status Register Out
High Impedance
MSB
7
6543210
Status Register Out
MSB
7



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