AT25DF021A-MHNHR-T datasheet(32/59 Pages) RENESAS

32 / 59 page

DS-AT25DF021A-042 Rev. L

Page 32

8/7/23

AT25DF021A Datasheet

When the SPRL bit is in the logical 0 state, all Sector Protection Registers are unlocked and can be modified (the

Protect Sector and Unprotect Sector commands, as well as the Global Protect and Global Unprotect features, are

processed as normal). The SPRL bit defaults to the logical 0 state after a power-up or a device reset.

The SPRL bit can be modified freely whenever the WP pin is deasserted. However, if the WP pin is asserted, then

the SPRL bit can only be changed from a logical 0 (Sector Protection Registers are unlocked) to a logical 1

(Sector Protection Registers are locked). In order to reset the SPRL bit back to a logical 0 using the Write Status

can be user modified through the Write Status Register command.

11.1.2

SPM Bit

The SPM bit indicates whether the device is in the Byte/Page Program mode or the Sequential Program Mode.

The default state after power-up or device reset is the Byte/Page Program mode.

11.1.3

EPE Bit

The EPE bit indicates whether the last erase or program operation completed successfully or not. If at least one

byte during the erase or program operation did not erase or program properly, then the EPE bit is set to the logical

1 state. The EPE bit is not set if an erase or program operation stops for any reason such as an attempt to erase

or program a protected region or if the WEL bit is not set prior to an erase or program operation. The EPE bit is

updated after every erase and program operation.

11.1.4

WPP Bit

The WPP bit can be read to determine if the WP pin has been asserted or not.

11.1.5

SWP Bits

The SWP bits provide feedback on the software protection status for the device. There are three possible

combinations of the SWP bits that indicate whether none, some, or all of the sectors have been protected using

the Protect Sector command or the Global Protect feature. If the SWP bits indicate that some of the sectors have

been protected, then the individual Sector Protection Registers can be read with the Read Sector Protection

Registers command to determine which sectors are in fact protected.

11.1.6

WEL Bit

The WEL bit indicates the current status of the internal Write Enable Latch. When the WEL bit is in the logical 0

state, the device does not accept any program, erase, Protect Sector, Unprotect Sector, or Write Status Register

commands. The WEL bit defaults to the logical 0 state after a device power-up or reset. Also, the WEL bit is reset

to the logical 0 state automatically under the following conditions:

▪ Write Disable operation completes successfully

▪ Write Status Register operation completes successfully or stops

▪ Protect Sector operation completes successfully or stops

▪ Unprotect Sector operation completes successfully or stops

▪ Byte/Page Program operation completes successfully or stops

▪ Sequential Program Mode reaches highest unprotected memory location

▪ Sequential Program Mode reaches the end of the memory array

▪ Sequential Program Mode stops

▪ Block Erase operation completes successfully or stops

▪ Chip Erase operation completes successfully or stops

▪ Hold condition stops

If the WEL bit is in the logical 1 state, it is not reset to a logical 0 if an operation stops due to an incomplete or

unrecognized opcode being clocked into the device before the CS pin is deasserted. In order for the WEL bit to be

AT25DF021A-MHNHR-T Datenblatt(PDF) 32 Page - Renesas Technology Corp

AT25DF021A-MHNHR-T Datenblatt(HTML) 32 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

Datenblatt Download

Link URL