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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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AT25DF021A-MHNHR-T Datenblatt(PDF) 12 Page - Renesas Technology Corp |
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AT25DF021A-MHNHR-T Datenblatt(HTML) 12 Page - Renesas Technology Corp |
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12 / 59 page  DS-AT25DF021A-042 Rev. L Page 12 8/7/23 © 2023 Renesas Electronics AT25DF021A Datasheet 6. Commands and Addressing A valid command or operation must always be started by first asserting the CS pin. After the CS pin has been asserted, the host controller must then clock out a valid 8-bit opcode on the SPI bus. Following the opcode, command-dependent information, such as address and data bytes, are then clocked out by the host controller. All opcode, address, and data bytes are transferred with the most-significant bit (MSB) first. An operation is ended by deasserting the CS pin. Opcodes not supported by the AT25DF021A are ignored by the device and no operations are started. The device continues to ignore any data presented on the SI pin until the start of the next operation (CS pin being deasserted and then reasserted). Also, if the CS pin is deasserted before complete opcode and address information is sent to the device, then no operation is performed and the device simply returns to the idle state and wait for the next operation. Addressing of the device requires a total of three bytes of information to be sent, representing address bits A23- A0. Since the upper address limit of the AT25DF021A memory array is 00FFFFh, address bits A23-A16 are always ignored by the device. Table 2. Command Listing Command Opcode Clock Frequency Address Bytes Dummy Bytes Data Bytes Read Commands Read Array 0Bh 0000 1011 Up to 104 MHz 3 1 1+ 03h 0000 0011 Up to 33 MHz[1] 3 0 1+ Dual Output Read 3Bh 0011 1011 Up to 104 MHz 3 1 1+ Program and Erase Commands Page Erase 81h 1000 0001 Up to 104 MHz 3 0 0 Block Erase (4 kBytes) 20h 0010 0000 Up to 104 MHz 3 0 0 Block Erase (32 kBytes) 52h 0101 0010 Up to 104 MHz 3 0 0 Block Erase (64 kBytes) D8h 1101 1000 Up to 104 MHz 3 0 0 Chip Erase 60h 0110 0000 Up to 104 MHz 0 0 0 C7h 1100 0111 Up to 104 MHz 0 0 0 Byte/Page Program (1 to 256 Bytes) 02h 0000 0010 Up to 104 MHz 3 0 1+ Sequential Program Mode ADh 1010 1101 Up to 104 MHz 3, 0[2] 0 1 AFh 1010 1111 Up to 104 MHz 3, 0[2] 0 1 Dual-Input Byte/Page Program (1 to 256 bytes) A2h 1010 0010 Up to 104 MHz 3 0 1+ Protection Commands Write Enable 06h 0000 0110 Up to 104 MHz 0 0 0 Write Disable 04h 0000 0100 Up to 104 MHz 0 0 0 Protect Sector 36h 0011 0110 Up to 104 MHz 3 0 0 Unprotect Sector 39h 0011 1001 Up to 104 MHz 3 0 0 Read Sector Protection Registers 3Ch 0011 1100 Up to 104 MHz 3 0 1+ Security Commands Program OTP Security Register 9Bh 1001 1011 Up to 104 MHz 3 0 1+ Read OTP Security Register 77h 0111 0111 Up to 104 MHz 3 2 1+ Status Register Commands Read Status Register 05h 0000 0101 Up to 104 MHz 0 0 1+ Active Status Interrupt 25h 0010 0101 Up to 104 MHz 0 1 0 Write Status Register Byte 1 01h 0000 0001 Up to 104 MHz 0 0 1 Write Status Register Byte 2 31h 0011 0001 Up to 104 MHz 0 0 1 |
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