MM2201VM1TR datasheet(7/15 Pages) STMICROELECTRONICS

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SCL

SDA

SCL

SDA

START

CONDITION

SDA

INPUT

SDA

CHANGE

AI00792

STOP

CONDITION

MSB

ACK

START

CONDITION

SCL

MSB

ACK

STOP

CONDITION

Figure 6. I2C Bus Protocol

Byte Write. In the Byte Write mode the master

sends one data byte, which is acknowledged by the

memory. The master then terminates the transfer

by generating a STOP condition.

Page Write. The Page Write mode allows up to 4

bytes to be written in a single write cycle, provided

that they are all located in the same ’row’ in the

memory: that is the 5 most significant memory

address bits (A6-A2) are the same. The master

sends from one up to four bytes of data, which are

each acknowledged by the memory. After each

byte is transfered, the internal byte address counter

(2 least significant bits only) is incremented. The

transfer is terminated by the master generating a

STOP condition. Care must be taken to avoid ad-

dress counter ’roll-over’ which could result in data

being overwritten.

It must be noticed that, for any write mode, the

generation by the master of the STOP condition

starts the internal memory program cycle. All inputs

are disabled until the completion of this cycle and

the memory will not respond to any request.

Minimizing System Delays by Polling On ACK.

During the internal write cycle, the memory discon-

nects itself from the bus in order to copy the data

from the internal latches to the memory cells. The

maximum value of the write time (tW) is given in the

AC Characteristics table, since the typical time is

shorter, the time seen by the system may be re-

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