Symbol

Alt

Parameter

Min

Max

Unit

Clock Rise Time

1

µs

Clock Fall Time

300

ns

Input Rise Time

1

µs

Input Fall Time

300

ns

(1)

Clock High to Input Transition

4.7

µs

Clock Pulse Width High

4

µs

Input Low to Clock Low (START)

4

µs

Clock Low to Input Transition

0

µs

Clock Pulse Width Low

4.7

µs

Input Transition to Clock Transition

250

ns

Clock High to Input High (STOP)

4.7

µs

Input High to Input Low (Bus Free)

4.7

µs

(2)

Clock Low to Next Data Out Valid

0.3

3.5

µs

Data Out Hold Time

300

ns

Clock Frequency

100

kHz

Write Time

10

ms

Notes: 1. For a reSTART condition, or following a write cycle.

2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP

conditions.

Table 5. AC Characteristics

Memory Addressing. To start communication be-

tween the bus master and the slave M2201, the

master must initiate a START condition. Following

this, the master sends onto the SDA bus line 8 bits

(MSB first) corresponding to the 7th bit byte-ad-

dress and a READ or WRITE bit. This 8th bit is set

to ’1’ for read and ’0’ for write operations. If a match

is found, the corresponding memory will acknow-

ledge the identification on the SDA bus during the

9th bit time.

Write Operations

Following a START condition the master sends the

byte address with the RW bit reset to ’0’. The

memory acknowledges this and waits for a data

byte. Any write command with WC = 1 (during a

period of time from the START condition until the

end of the Byte Address) will not modify data and

will NOT be acknowledged on data bytes, as in

Figure 8.

Input Rise and Fall Times

≤ 50ns

Input Pulse Voltages

Input and Output Timing Ref.

Voltages

Table 6. AC Measurement Conditions

AI00825

0.8VCC

0.2VCC

0.7VCC

0.3VCC

Figure 4. AC Testing Input Output Waveforms

5/15

M2201