AS7038RB datasheet(79/127 Pages) AMSOSRAM

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AS7038RB

Functional Description

Datasheet

• PUBLIC

DS000726

• v2-00 • 2021-Jun-02

126

│ 78

Addr: 0x28

LTF_CONTROL

Bit

Bit Name

Default

Access

Bit Description

ltf_start

R_PUSH

Writing 1 starts the counter, and it will run for

the specified time (itime). Afterwards it stops

automatically and interrupt is flagged.

writing 0 to the counter stops it as well.

reading the value returns whether the counter

is running.

If ltf_fifo_mode is non-zero, then FM

conversions are done continuously until a 0 is

written to this bit again.

AZ_CONTROL (Address 0x29)

Figure 96:

AZ_CONTROL Register

Addr: 0x29

AZ_CONTROL

Bit

Bit Name

Default

Access

Bit Description

7:2

Do not use

RW_SM

Do not use

az_enable_1

RW_SM

Writing a '1' to this register starts the AZ

engine for channel 1. This is usually not

necessary, as AZ is executed automatically

before the first LTF integration (unless

az_disable_auto is set) The bit is cleared to '0'

automatically when the AZ has finished. You

cannot write a '0' to this register.

az_enable_0

RW_SM

The same as az_enable_1, but for channel 0.

OFFSET0 (Address 0x2a)

Figure 97:

OFFSET0 Register

Addr: 0x2a

OFFSET0

Bit

Bit Name

Default

Access

Bit Description

7:0

offset0[7:0]

RW_SM

This register holds the value of the offset on the

channel 0 OpAmp. It can be overwritten, and it

gets overwritten by the auto-zero mechanism. The

value is in sign/magnitude encoding.

The value is ±127, sign/magnitude

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