ST10F168 datasheet(14/74 Pages) STMICROELECTRONICS

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ST10F168

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5.1 - Programming / Erasing with ST

Embedded Algorithm Kernel

There are three stages to run STEAK :

– To load the registers R0 to R4 with the STEAK

command, the address and the data to be pro-

gramed, or sector to be erased. Table 4 gives

the STEAK parameters for each type of Flash

programming / erasing operation. Table 5 de-

fines the codes used in Table 4.

– To initiate the Unlock Sequence. The Unlock Se-

quence is composed of two consecutive writes

to an even address in the Flash active address

space - the first write has direct addressing

mode (MOV mem, Rwn) - the second write has

indirect addressing mode (MOV [Rwm], Rwn).

Rwn can be any unused Word-GPR (R6 to R15)

loaded with a value resulting in the same even

address as “mem”.

– To read the return values in R0. When the em-

bedded programming / erasing algorithm returns

to trigger point, return values are given in R0.

Table 6 gives the error-code definitions, Table 7

gives the return values in each register for each

type of Flash programming / erasing command.

Note: The Flash Embedded STEAK Algorithms

require at least 50 words on the Internal

System Stack. STEAK verifies that there is

enough free space on the System Stack,

before performing a programming or eras-

ing operation.The MDH, MDL and MDC

Code examples for programming and erasing the

Flash

Memory

using

STEAK

are

given

Section 5.2.

Note

For more details refer to STEAK applica-

tion note on www.st.com web site.

Table 4 : STEAK parameters

Command

Single Word programming

55Ash

AddOff

2TCL

Double Word programming

DD4sh

AddOff

DWL

DWH

2TCL

Multiple (block) programming

AA5sh

BegAddOff

EndAddOff

SourceAddr

2TCL

Sector Erasing

EEEEh

5555h

Bnk

2TCL

Set Flash Protection UPROG bit

CCCCh

5555h

3333h

AAAAh

2TCL

Read Status

7777h

2TCL

Table 5 : Programming / erasing code definition

Segment of the Target Flash Memory cell,

AddOff

Segment Offset of the Target Flash Memory cell. Must be even value (Word-aligned address).

Data (Word) to be written in Flash.

DWL,DWH Data (double Word, DHL = low Word, DWH = high Word) to be written in Flash.

BegAddOff

Segment Offset of the FIRST Target Flash Memory Word to be written in a Multiple programming

command. Must be even value (Word-aligned address).

EndAddOff

Segment Offset of the LAST Target Flash Memory Word to be written in a Multiple programming

command.

Must be even value (Word-aligned address). The value D = (EndAddOff - BegAddOff) must be:

0 <= D < 16384 (ie. up to one page (16K Byte) can be written in the flash with one multi-Word

programming command).

SourceAdd

Start address for the block to be programmed.

This address is using implicitly the data paging mechanism of the CPU. SourceAdd value must respect

the following rules :

- SourceAdd + (EndAddOff - BegAddOff) < 16384.

- Page 0 and 1 can NOT be used for source data if bit ROMS1 = ‘1’ (in SYSCON register).

Note that source data can be located in Flash (In pages 0, 1, 6 to 19 if bit ROMS1 = ‘0’, or in pages 4 to 19

if bit ROMS1 = ‘1’).

Bnk

Number of the Bank to be erased. For security, R2 and R3 must hold the same value.

2TCL

CPU clock period in nano-seconds (eg. R4 = 50 (32h) means CPU frequency is 20MHz).

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