ST10F168 datasheet(18/74 Pages) STMICROELECTRONICS

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ST10F168

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5.3 - Flash Memory Configuration

The

default

memory

configuration

the

ST10F168 Memory is determined by the state of

the EA pin at reset. This value is stored in the

Internal ROM Enable bit : ROMEN of the

SYSCON Register.

When ROMEN = 0, the internal FLASH is disabled

and external ROM is used for startup control.

Flash memory can be enabled later by setting the

ROMEN bit of SYSCON to 1. Ensure that the

code which performs this setting is NOT running

from external ROM in a segment that will be

replaced by FLASH memory, otherwise unex-

pected behaviour may occur.

For example, if the external ROM code is located

in the first 32K Byte of segment 0, the first

32K Byte of the FLASH must then be enabled in

segment 1. This is done by setting the ROMS1 bit

of SYSCON to 0, before or simultaneously with

setting the ROMEN bit. This must be done in the

externally supplied program, before the execution

of the EINIT instruction. If program execution

starts from external memory, but the Flash mem-

ory mapped in segment 0 is accessed later, then

the code that sets the ROMEN bit must be exe-

cuted either in segment 0 but above address

00’8000h, or from the internal RAM.

Bit ROMS1 only affects the mapping of the first

32K Byte of the Flash memory. All other parts of

the

Flash

memory

(addresses

01’8000h

04’FFFFh) remain unaffected.

Note: The SGTDIS Segmentation Disable /

Enable must also be set to 0 to enable the use of

the full 256K Byte of on-chip memory in addition

to the external boot memory. The correct proce-

dure for changing the segmentation registers

must be observed to prevent an unwanted trap

condition :

– Instructions that configure the internal memory

must only be executed from external memory or

from the internal RAM.

– An

Absolute

Inter-Segment

Jump

(JMPS)

instruction must be executed after Flash enabling,

before the next instruction, even if the next

instruction is located in the consecutive address.

– Whenever the internal memory is disabled, ena-

bled or remapped, the DPPs must be explicitly

(re)loaded to enable correct data accesses to

the internal memory and / or external memory.

5.4 - Flash Protection

If Flash Protection is active, data operands in the

on-chip Flash Memory area can only be read by a

program executed from the Flash Memory itself.

Program branches from or into the on-chip Flash

memory are possible in the Flash protection

mode. Erasing and programming of the Flash

memory is not possible as long as protection is

active.

Flash protection is controlled by the Protection

UPROM Programming Bit (UPROG). UPROG is a

'hidden' one-time programmable bit only accessi-

ble in a special mode which can be entered via a

Flash EPROM programming board for example. If

UPROG is set to "1", Flash protection is active

after reset. By default Flash Protection is disabled

(UPROG=0).

When flash protection is active (the default after

reset if UPROG bit is set), then any read access in

the flash by a code executed from external or

internal RAM (IRAM or XRAM) will return the

value 0B88Bh. Any call of STEAK will return the

error code ‘01’ (Protected flash).

Normally Flash protection should never be deacti-

vated, once activated. If this has to be done, for

example because the Flash memory has to be

reprogrammed with updated program / variables,

a zero value has to be written at any even address

in the active address space of the Flash memory.

This write can be done only by an instruction exe-

cuted from the internal Flash Memory itself.

For example:

MOV FLASH,ZEROS ; Deactivate Flash

Protection.

; Flash is any even address in Flash

memory space. This instruction MUST

be executed from Flash memory itself.

After this instruction, the flash is temporarily

de-protected, thus any read access of the flash

from code executed from external memory or

internal RAMs will be correctly executed, and calls

of STEAK can be correctly performed (program-

ming, erasing or status reading).

Note: 1. That all STEAK commands re-activate

the flash protection if bit UPROG is set

when completed.

5.5 - Bootstrap Loader Mode

Pin P0L.4 (BSL) activates the on-chip bootstrap

loader, when low during hardware reset. The

bootstrap loader allows moving the start code into

the internal RAM of the ST10F168 via the serial

interface ASC0. The ST10F168 will remain in

bootstrap loader mode until a hardware reset with

P0L.4 high or a software reset occurs. The boot-

straps loader acknowledge byte is D5h.

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