TDA7333N datasheet(29/36 Pages) STMICROELECTRONICS

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TDA7333N

Functional description

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Read only the first register rds_int to check the “bne” bit.

If “bne” bit is not set, the stop condition can be set, as shown in (Figure 15).

If “bne” bit is set, the transfer must be continued by the i2c master, until at least the four

allowed to set the stop condition (Figure 14). Then the whole Buffer must be read out,

by reading each time at least the five registers rds_int, rds_qu, rds_corrp, rds_bd_h

and rds_bd_l without interruption. This must be done until the “bne” bit is set to zero

(last RDS block).

If the I2C master is not able to handle the above protocol, it must read always at least

the first five registers rds_int, rds_qu, rds_corrp, rds_bd_h, rds_bd_l out independent if

“bne” is set or not (Figure 14). If the “bne” flag is set the whole RAM buffer must be

read out, by reading each time at least the five registers rds_int, rds_qu, rds_corrp,

rds_bd_h and rds_bd_l without interruption. This must be done until the “bne” bit is set

to zero (last RDS block).

Note:

In polling mode the interrupt flag “int” is just a indication that the wanted information is stored

within the RAM Buffer.

In polling mode it is possible that the last RDS data (rds_qu, rds_corrp, rds_bd_h and

rds_bd_l), which was read out as the “bne” flag was set to zero, is identical to the RDS data

before. This must be checked by the external micro controller by comparing the last received

2 RDS blocks. If they are identical, one of them can be skipped. (This is the case if just one

RDS block is stored in the RAM buffer).

Figure 14.

I2C read access example 1: read of 5 bytes

Figure 15.

I2C read access example 2: read of 1 byte

SDA

SCL

START

CONDITION

R ACK

rds_int[7:0]

rds_qu[7:0]

ACK

CSN 1

SLAVE ADDRESS

rds_corrp[7:0]

rds_bd_h[7:0]

rds_bd_l[7:0]

STOP

CONDITION

ACK

SDA

SCL

START

CONDITION

ACK

rds_int[7:0]

CSN 1

SLAVE ADDRESS

STOP

CONDITION

ACK

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