ST6391 datasheet(19/68 Pages) STMICROELECTRONICS

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DRBR

Data RAM

Bank Register

(E8h, Write Only)

D7 D6 D5 D4 D3 D2 D1 D0

DRBR0

DRBR1

DRBR2

DRBR3

DRBR4

DRBR5

DRBR6

DRBR7

Figure 18. Data RAM Bank Register

MEMORY SPACES (Continued)

Data RAM/EEPROM/OSD RAM Addressing

In all members of the ST639x family 64 bytes of data

RAM are directly addressablein the data space from

80h to BFh addresses. The additional 192 bytes of

RAM, the 384 bytes of EEPROM , and the OSD

RAM can be addressed using the banks of 64

bytes located between addresses 00h and 3Fh.

The selection of the bank is done by programming

the Data RAM Bank Register (DRBR) located at

the E8h address of the Data Space. In this way

each bank of RAM, EEPROM or OSD RAM can se-

lect 64 bytes at a time. No more than one bank

should be set at a time.

DRBR Value

Selection

Hex.

Binary

01h

0000 0001

EEPROM Page 0

All devices

02h

0000 0010

EEPROM Page 1

03h

0000 0011

EEPROM Page 2

ST6395 and ST6397

ONLY

81h

1000 0001

EEPROM Page 3

82h

1000 0010

EEPROM Page 4

83h

1000 0011

EEPROM Page 5

04h

0000 0100

RAM Page 2

All devices

08h

0000 1000

RAM Page 3

10h

0001 0000

RAM Page 4

20h

0010 0000

OSD Page 5

40h

0100 0000

OSD Page 6

Table 5. Data RAM Bank Register Set-up

DRBR7,DRBR1,DRBR0. These bits select the

EEPROM page s.

DRBR6, DRBR5. Each of these bits, when set, will

select one OSD RAM register page.

DRBR4,DRBR3,DRBR2. Each of these bits, when

set, will select one RAM page.

This register is undefined after reset.

Table 5 summarizes how to set the Data RAM

Bank Register in order to select the various banks

or pages.

Note :

Care is required when handling the DRBR as it is

write only. For this reason, it is not allowed to

change the DRBR contents while executing inter-

rupts drivers, as the driver cannot save and than

restore its previous content. If it is impossible to

avoid the writing of this register in interrupts driv-

ers, an image of this register must be saved in a

RAM location, and each time the program writes

the DRBR it writes also the image register.

The image register must be written first, so if an in-

terrupt occurs between the two instructions the

DRBR is not affected.

ST6391,92,93,95,97,99

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