ST6391 datasheet(35/68 Pages) STMICROELECTRONICS

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Figure 37. Hardware Activated Watchdog Block Diagram

Figure 38. Hardware Activated Watchdog

Working Principle

HARDWARE ACTIVATED DIGITAL WATCH-

DOG FUNCTION

The hardware activated digital watchdogfunction con-

sists of a down counter that is automatically initialized

after reset so that this function does not need to be ac-

tivated by the user program. As the watchdog function

is always activated this down counter can not be used

as a timer. The watchdogis using onedata space reg-

ister (HWDR location D8h). The watchdog register is

set to FEh on reset and immediately starts to count

down, requiring no software start. Similarly the hard-

ware activated watchdog can not be stopped or de-

layed by software.

The watchdog time can be programmed using the 6

MSbits in the watchdog register, this gives the possi-

bility to generate a reset in a time between 3072 to

196608oscillator cycles in 64 possible steps. (With a

clock frequency of 8MHz this means from 384

µsto

24.576ms). The reset is prevented if the register is

reloaded with the desired value before bits 2-7 de-

crement from all zeros to all ones.

The presence of the hardware watchdog deactivates

the STOP instruction and a WAIT instruction is auto-

matically executed instead of a STOP. Bit 1 of the

watchdog register (set to one at reset) can be used to

generatea software reset if cleared to zero). Figure 37

shows the watchdog block diagram while Figure 38

shows its working principle.

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