ST7SCR datasheet(22/102 Pages) STMICROELECTRONICS

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ST7SCR

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6.2 RESET SEQUENCE MANAGER (RSM)

6.2.1 Introduction

The reset sequence manager has two reset sourc-

es:

Internal LVD reset (Low Voltage Detection)

which includes both a power-on and a voltage

drop reset

Internal watchdog reset generated by an

internal watchdog counter underflow as shown

in Figure 14.

6.2.2 Functional Description

The reset service routine vector is fixed at ad-

dresses FFFEh-FFFFh in the ST7 memory map.

The basic reset sequence consists of 3 phases as

shown in Figure 13:

A first delay of 30µs + 127 tCPU cycles during

which the internal reset is maintained.

A second delay of 512 tCPU cycles after the

internal reset is generated. It allows the

oscillator to stabilize and ensures that recovery

has taken place from the Reset state.

Reset vector fetch (duration: 2 clock cycles)

Low Voltage Detector

The low voltage detector generates a reset when

VDD<VIT+ (rising edge) or VDD<VIT- (falling edge),

as shown in Figure 13.

The LVD filters spikes on VDD larger than tg(VDD) to

avoid parasitic resets. See “SUPPLY AND RESET

CHARACTERISTICS” on page 79.

Figure 13. LVD RESET Sequence

Figure 14. Watchdog RESET Sequence

DELAY 1

RUN

LVD

RESET

FETCH VECTOR (2 tCPU)

DELAY 2

LVD

RESET

INTERNAL

RESET

DELAY 1 = 30µs + 127 tCPU

DELAY 2 = 512 tCPU

VDD

VIT+

VIT-

WATCHDOG

WATCHDOG UNDERFLOW

RESET

FETCH VECTOR (2 tCPU)

DELAY 1

WATCHDOG

RESET

DELAY 2

DELAY 1 = 30µs + 127 tCPU

DELAY 2 = 512 tCPU

RUN

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