PM6680 datasheet(43/49 Pages) STMICROELECTRONICS

43 / 49 page

PM6680

Device description

43/49

Equation 39

(Let's assume the maximum temperature Tmax = 75 °C in RDSon calculation)

OUT2:

Equation 40

Equation 41

(Let's assume Tmax = 75 °C in RDSon calculation)

Input capacitor

Maximum input capacitor RMS current is about 2.8 A. Then ICinRMS > 2.8 A.

We put three 10 uF ceramic capacitors with Irms = 1.5 A.

Synchronous rectifier

OUT1: Shottky diode STPS1L30M

OUT2: Shottky diode STPS1L30M

Integrator loop

(Refer to Figure 37)

OUT1: The ripple is smaller than 40mV, then the virtual ESR network is required.

CINT = 1 nF; Cfilt = 47 pF; RINT =1 kΩ

C = 5.6 nF; R= 36 k

Ω; R1 = 3 kΩ

OUT2: The ripple is smaller than 40 mV, then the virtual ESR network is required.

CINT = 1 nF; Cfilt = 110pF; RINT = 1 kΩ

C = 5.6 nF; R = 22 k

Ω; R1 = 3.3 kΩ

Output feedback divider

(Refer to Figure 30 on page 24)

OUT1: R1 = 10 k

Ω; R2 = 6.8 kΩ

OUT2: R1 = 11 k

Ω; R2 = 1.8 kΩ

Layout guidelines

The layout is very important in terms of efficiency, stability and noise of the system. It is

possible to refer to the PM6680 demoboard for a complete layout example.

For good PC board layout follows these guidelines:

●

Place on the top side all the power components (inductors, input and output capacitors,

MOSFETs and diodes). Refer them to a power ground plan, PGND. If possible, reserve

a layer to PGND plan. The PGND plan is the same for both the switching sections.

●

AC current paths layout is very critical (see Figure 41 on page 44). The first priority is to

minimize their length. Trace the LS MOSFET connection to PGND plan as short as

Ω

≈

Ω

⋅

≡

670

100

RCSENSE

(min)

(max)

(min)

LOAD

Lvalley

∆

−

Ω

≈

Ω

⋅

≡

680

100

RCSENSE

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