STLS2F01 datasheet(6/48 Pages) STMICROELECTRONICS

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Introduction

STLS2F01

6/48

Introduction

STLS processors are based on the Loongson CPU architecture licensed by

STMicroelectronics from the Institute of Computing Technology (ICT), which is part of the

Chinese Academy of Science. The STLS family belongs to the 64-bit high-end processors

for applications requiring high level of performance and efficiency in terms of cost, power

consumption and area.

Loongson CPU architecture is compatible in user mode at the MIPS III level of the MIPS

64-bit architecture.

This microprocessor achieves one of the top positions in the MIPS family for the

combination of multiple features: high clock frequency, out-of-order superscalar execution

and ability to run single-instruction-multiple data (SIMD).

STLS processors implement a superscalar, out-of-order execution pipeline with dynamic

branch prediction and non-blocking cache.

Figure 1.

Block diagram

L2 cache

DDR2

333MHz DDR

Controller

Cache Interface

Writeback

Queue

Miss

Queue

Refill Bus

Branch Bus

BTB

BHT

BRQ

Fix

Float

Integer

File

Floating

Point

File

Map Bus

ROQ

ALU1

ALU2

AGU

FPU1

TLB

CP0

Queue

D-Cache

64KB

FPU2

ITLB

I-Cache

64KB

Commit Bus

Writeback Bus

Reorder Queue

AXI Crossbar

133MHz PCI-X Local IO GPIO, INT

I/O Controller

AC00117

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