| Datenblatt-Suchmaschine für elektronische Bauteile |
|
STLS2F02 Datenblatt(PDF) 40 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STLS2F02 Datenblatt(HTML) 40 Page - STMicroelectronics |
|
40 / 49 page ![]() Electrical characteristics STLS2F02 40/49 6.4 AC parameters Table 17. Clock parameters (Test conditions:SYSCLK=100 MHz, PCICLK=133 MHz, MEMCLK=333 MHz, CoreClk=1000 MHz) Parameter Min Typ Max Unit SYSCLK high level time 2 5 8 ns SYSCLK low level time 2 8 ns SYSCLK rising time 1 1 ns SYSCLK falling time 1 1 ns SYSCLK cycle variation ±300 ps PCI_CLK high level time 3 ns PCI_CLK low level time 3 ns PCI_CLK rising slew 1.5 V/ns PCI_CLK falling slew 1.5 V/ns PCI_CLK cycle variation ±500 ps MEMCLK high level time 1.41 1.59 ns MEMCLK low level time 1.41 1.59 ns MEMCLK rising slew 1 V/ns MEMCLK falling slew 1 V/ns MEMCLK cycle variation ±225 ps DQS high level time 1.35 1.65 ns DQS low level time 1.35 1.65 ns DQS rising slew 1 V/ns DQS falling slew 1 V/ns DQS cycle variation ±225 ps Table 18. Input setup and hold time (Test conditions:SYSCLK=100 MHz, PCICLK=133 MHz, MEMCLK=333 MHz, CoreClk=1000 MHz) Parameter Min Typ Max Unit PCI_* signals setup time 1.2 ns PCI_* signals hold time 0.5 ns LIO_* signals setup time 1.2 ns LIO_* signals hold time 0.5 ns DDR2_DQ*/CB* signals setup time 0.1 ns DDR2_DQ*/CB* signals hold time 0.175 ns |
|
Link URL |
| War ALLDATASHEET hilfreich? [ DONATE ] |
Über Alldatasheet | Werbung | Kontakt | Privatsphäre und Datenschutz | Link zum Datenblatt | Linktausch | Hersteller All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |