H8SXSLASH1663 datasheet(406/1158 Pages) RENESAS

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Section 7 DMA Controller (DMAC)

Rev.1.00 Jun. 07, 2006 Page 354 of 1102

REJ09B0294-0100

(3) Activation by External Request

A transfer is started by a transfer request signal (

DREQ) from an external device. When a DMA

transfer is enabled (DTE = 1), the DMA transfer is started by the

DREQ assertion. When a DMA

transfer between on-chip peripheral modules is performed, select an activation source from the

auto request and on-chip module interrupt (the external request cannot be used).

A transfer request signal is input to the

DREQ pin. The DREQ signal is detected on the falling

edge or low level. Whether the falling edge or low level detection is used is selected by the

DREQS bit in DMDR. To perform a block transfer, select the low level detection (DREQS = 0).

When an external request is selected as an activation source, clear the DDR bit to 0 and set the

ICR bit to 1 for the corresponding pin. For details, see section 9, I/O Ports.

7.5.4

Bus Access Modes

There are two types of bus access modes: cycle stealing and burst.

When an activation source is the auto request, the cycle stealing or burst mode is selected by bit

DTF0 in DMDR. When an activation source is the on-chip module interrupt or external request,

the cycle stealing mode is selected.

(1) Cycle Stealing Mode

In cycle stealing mode, the DMAC releases the bus every time one unit of transfers (byte, word,

longword, or 1-block size) is completed. After that, when a transfer is requested, the DMAC

obtains the bus to transfer 1-unit data and then releases the bus on completion of the transfer. This

operation is continued until the transfer end condition is satisfied.

When a transfer is requested to another channel during a DMA transfer, the DMAC releases the

bus and then transfers data for the requested channel. For details on operations when a transfer is

requested to multiple channels, see section 7.5.8, Priority of Channels.

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