H8SXSLASH1663 datasheet(517/1158 Pages) RENESAS

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Section 9 I/O Ports

Rev.1.00 Jun. 07, 2006 Page 465 of 1102

REJ09B0294-0100

(7) PB1/

CS1/CS2-B/CS5-A/CS6-B/CS7-B

The pin function is switched as shown below according to the combination of operating mode,

EXPE bit, port function control register (PFCR), and the PB1DDR bit settings.

Setting

I/O Port

Module Name

Pin Function

CS1_OE

CS2B_OE CS5A_OE CS6B_OE CS7B_OE PB1DDR

CS1 output*



CS2-B output*



CS5-A output*



CS6-B output*



Bus controller

CS7-B output*



PB1 output

I/O port

PB1 input

(initial setting)

Note:

Valid in external extended mode (EXPE = 1)

(8) PB0/

CS0/CS4/CS5-B

The pin function is switched as shown below according to the combination of operating mode,

EXPE bit, port function control register (PFCR), and the PB0DDR bit settings.

Setting

I/O Port

Module Name

Pin Function

CS0_OE

CS4_OE

CS5B_OE

PB0DDR

CS0 output

(initial setting E)



CS4 output



Bus controller

CS5-B output



PB0 output

I/O port

PB0 input

(initial setting S)

[Legend]

Initial setting E:

Initial setting in on-chip ROM disabled external extended mode

Initial setting S:

Initial setting in other modes

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