H8SXSLASH1663 datasheet(528/1158 Pages) RENESAS

528 / 1158 page

Section 9 I/O Ports

Rev.1.00 Jun. 07, 2006 Page 476 of 1102

REJ09B0294-0100

Table 9.5

Available Output Signals and Settings in Each Port

Port

Output

Specification

Signal Name

Output

Signal

Name

Signal Selection

Peripheral Module Settings

SCL0_OE

SCL0

ICCRA.ICE = 1

DACK1A_OE

DACK1 PFCR7.DMAS1[A,B] = 00 DACR.AMS = 1, DMDR.DACKE = 1

SDA0_OE

SDA0

ICCRA.ICE = 1

TEND1A_OE

TEND1 PFCR7.DMAS1[A,B] = 00 DMDR.TENDE = 1

SCL1_OE

SCL1

ICCRA.ICE = 1

TxD5_OE

TxD5

SCR.TE = 1, IrCR.IrE = 0

IrTxD5_OE

IrTxD5

SCR.TE = 1, IrCR.IrE = 1

SDA1_OE

SDA1

ICCRA.ICE = 1

—

DACK0A_OE

DACK0 PFCR7.DMAS0[A,B] = 00 DACR.AMS = 1, DMDR.DACKE = 1

SCK2_OE

SCK2

When SCMR.SMIF = 1:

SCR.TE = 1 or SCR.RE = 1 while

SMR.GM = 0, SCR.CKE [1, 0] = 01 or while

SMR.GM = 1

When SCMR.SMIF = 0:

SCR.TE = 1 or SCR.RE = 1 while

SMR.C/A = 0, SCR.CKE [1, 0] = 01 or while

SMR.C/A = 1, SCR.CKE 1 = 0

TEND0A_OE

TEND0 PFCR7.DMAS0[A,B] = 00 DMDR.TENDE = 1

TxD2_OE

TxD2

SCR.TE = 1

TIOCB5_OE

TIOCB5

TPU.TIOR5.IOB3 = 0,

TPU.TIOR5.IOB[1,0] = 01/10/11

PO7_OE

PO7

NDERL.NDER7 = 1

TIOCA5_OE

TIOCA5

TPU.TIOR5.IOA3 = 0,

TPU.TIOR5.IOA[1,0] = 01/10/11

TMO1_OE

TMO1

TCSR.OS3,2 = 01/10/11 or

TCSR.OS[1,0] = 01/10/11

TxD1_OE

TxD1

SCR.TE = 1

PO6_OE

PO6

NDERL.NDER6 = 1

TIOCA4_OE

TIOCA4

TPU.TIOR4.IOA3 = 0,

TPU.TIOR4.IOA[1,0] = 01/10/11

PO5_OE

PO5

NDERL.NDER5 = 1

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