H8SXSLASH1663 datasheet(577/1158 Pages) RENESAS

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Section 10 16-Bit Timer Pulse Unit (TPU)

Rev.1.00 Jun. 07, 2006 Page 525 of 1102

REJ09B0294-0100

Table 10.26 TIORL_3

Description

Bit 3

IOC3

Bit 2

IOC2

Bit 1

IOC1

Bit 0

IOC0

TGRC_3

Function

TIOCC3 Pin Function

Output disabled

Initial output is 0 output

0 output at compare match

Initial output is 0 output

1 output at compare match

Initial output is 0 output

Toggle output at compare match

Output disabled

Initial output is 1 output

0 output at compare match

Initial output is 1 output

1 output at compare match

Output

compare

Initial output is 1 output

Toggle output at compare match

Capture input source is TIOCC3 pin

Input capture at rising edge

Capture input source is TIOCC3 pin

Input capture at falling edge

Capture input source is TIOCC3 pin

Input capture at both edges

Input

capture

Capture input source is channel 4/count clock

Input capture at TCNT_4 count-up/count-down

[Legend]

X: Don't care

Note:

When the BFA bit in TMDR_3 is set to 1 and TGRC_3 is used as a buffer register, this

setting is invalid and input capture/output compare is not generated.

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