H8SXSLASH1663R datasheet(345/1504 Pages) RENESAS

Teilenummer	H8SX/1663R

Bauteilbeschribung	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

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Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 313 of 1468

REJ09B0412-0200

9.11.7

Controlling Row Address Output Cycle

When the time between the ACTV command and the subsequent READ or WRIT command does

not meet a given specification, the Trw cycle in which the NOP command is output can be

inserted for one to three cycles between the Tr cycle in which the ACTV command is output and

the Tc1 cycle in which the column address is output. Set the bit according to the SDRAM to be

used and the frequency of this LSI so that the number of wait cycles can be optimal.

Figures 9.63 and 9.64 show a timing example when the one Trw cycle is inserted.

Address bus

Row address

Column address

SDRAM

Precharge-sel

RAS

CAS

CKE

PALL

ACTV

READ

NOP

DQMLU

DQMLL

D7 to D0

RD/

D15 to D8

Row

address

High

Figure 9.63 Read Timing Example of Row Address Output Retained for 1 Clock Cycle

(RCD1 = 0, RCD0 = 1, CAS Latency = 2)

H8SX/1663R Datenblatt(PDF) 345 Page - Renesas Technology Corp