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H8SX/1663R Datenblatt(PDF) 366 Page - Renesas Technology Corp |
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H8SX/1663R Datenblatt(HTML) 366 Page - Renesas Technology Corp |
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366 / 1504 page ![]() Section 9 Bus Controller (BSC) Rev. 2.00 Sep. 24, 2008 Page 334 of 1468 REJ09B0412-0200 For details on the software standby mode and deep software standby mode, see section 28, Power-Down Modes. EXTAL SDRAM φ Precharge-sel CS2 RAS CAS WE CKE Internal reset Address bus TRp TRr Deep software standby mode PSTOP0 set PSTOP0 clear IOKEEP clear Port setting PB1/ CS2 = H output setting PB5/CKE = L output setting Register setting in SDRAM (DRAMCR, etc.) REFCR, RTCNT, RTCOR Pin status saved with deep software standby mode (IOKEEP=1) Pin status depends on I/O port register Pin status in DRAM interface Figure 9.81 Self-Refresh Timing in Deep Software Standby Mode (TPC1 = 0, TPC0 = 0, RCW1 = 0, RCW0 = 0, RLW2 = 0, RLW1 = 0, RLW0 = 0) |
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