H8SXSLASH1663R datasheet(364/1504 Pages) RENESAS

Teilenummer	H8SX/1663R

Bauteilbeschribung	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

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Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 332 of 1468

REJ09B0412-0200

Some DRAMs with the self-refresh have a given time between cancellation of the self-refresh

mode and the subsequent command issued cycle. From one to seven of precharge cycles

immediately after cancellation of the self-refresh mode can be inserted. Normal precharge is also

performed according to bits TPC1 and TPC0 in DRACCR. Set the precharge time including the

normal precharge so that the precharge time immediately after a self-refresh cycle is optimal.

Figure 9.80 shows a timing example when one precharge cycle is added.

Address bus

Software

standby

SDRAM space write

Data bus

SDRAM

Precharge-sel

RAS

CAS

PALL

ACTV

WRITE

NOP

DQMLU, DQMLL

CKE

RD/

Row address

Column address

Row

address

Figure 9.80 Timing Example when 1 Precharge Cycle Added in the

Software Standby Mode (TPCS2 to TPCS0 = H'1, TPC1 = 0, TPC0 = 0)

H8SX/1663R Datenblatt(PDF) 364 Page - Renesas Technology Corp