H8SXSLASH1663R datasheet(365/1504 Pages) RENESAS

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Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 333 of 1468

REJ09B0412-0200

(b) Self-Refresh in Deep Software Standby Mode

The chip passes through the software standby mode in transitions to deep software standby mode.

The states of pins in software standby mode are retained in the deep software standby mode.

Therefore, the transition to self-refreshing is possible in deep software standby mode as well as in

software standby mode.

In deep software standby mode, initiate the transition to the self-refresh after having set the

IOKEEP bit in DPSBYCR to 1 as well as making the setting in "(a) Self-Refresh in Software

Standby Mode ".

On exit from deep software standby mode, use the following procedure to cancel self-refresh. (See

figure 9.81).

1. In PBDDR/PBDR, set PB1 (

CS2) as a high-level output and PB5(CKE) as a low-level

output.

Since the setting of the IOKEEP bit ensures retention of pin state at this time, the existing

state of high-level output on

CS2 and low-level output on is retained.

Set the PSTOP0 bit in SCKCR to1 and SDRAM

φ as a high level output. Since the setting

of the IOKEEP bit continues to ensure retention of pin state, the existing state of high-

level output on SDRAM

φ is retained.

Clear the IOKEEP bit in DPSBYCR.

This releases pin states from retention due to the setting of the IOKEEP bit, but the states

of pins

CS2, CKE, and SDRAMφ as set in steps 1and 2 do not change.

In the synchronous DRAM-related control registers that were initialized by the internal

reset that accompanied the transition to deep software standby mode, remake the settings

to enable the synchronous DRAM interface. At this time, do not make settings in REFCR,

RTCNT, and RTCOR.

Once the synchronous DRAM interface has been enabled, the state of the CKE pin

changes from low-level output to high-level output.

Restart output of the SDRAM

φ clock signal by clearing the PSTOP0 bit in SCKCR. This

restarts supply of SDRAM

φ to the synchronous DRAM.

Set REFCR, RTCNT, and RTCOR and enable refreshing.

As the state of the CKE pin has been changed in the step 4, adjust the time between the

state of change of the CKE pin and the next cycle of auto-refreshing in this procedure

within the stipulated refreshing interval of the synchronous DRAM.

Resume access to the synchronous DRAM.

Pre-charging time after the termination of self-refresh will be secured by the timing of the

setting in step 6.

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