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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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H8SX/1663R Datenblatt(PDF) 381 Page - Renesas Technology Corp |
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H8SX/1663R Datenblatt(HTML) 381 Page - Renesas Technology Corp |
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381 / 1504 page  Section 9 Bus Controller (BSC) Rev. 2.00 Sep. 24, 2008 Page 349 of 1468 REJ09B0412-0200 (1) Consecutive Reads in Different Areas If consecutive reads in different areas occur while bit IDLS1 in IDLCR is set to 1, idle cycles specified by bits IDLCA1 and IDLCA0 when bit IDLSELn in IDLCR is cleared to 0, or bits IDLCB1 and IDLCB0 when bit IDLSELn is set to 1 are inserted at the start of the second read cycle (n = 0 to 7). Figure 9.93 shows an example of the operation in this case. In this example, bus cycle A is a read cycle for ROM with a long output floating time, and bus cycle B is a read cycle for SRAM, each being located in a different area. In (a), an idle cycle is not inserted, and a conflict occurs in bus cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted, and a data conflict is prevented. Data hold time is long. Data conflict Bus cycle A Bus cycle B (a) No idle cycle inserted (IDLS1 = 0) (b) Idle cycle inserted B φ Address bus CS (area A) CS (area B) RD Data bus T 1 T 2 T 3 T 1 T 2 Bus cycle A Bus cycle B T 1 T 2 T 3 T 1 T i T 2 (IDLS1 = 1, IDLSELn = 0, IDLCA1 = 0, IDLCA0 = 0) Figure 9.93 Example of Idle Cycle Operation (Consecutive Reads in Different Areas) |
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