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H8SX/1663R Datenblatt(PDF) 377 Page - Renesas Technology Corp |
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H8SX/1663R Datenblatt(HTML) 377 Page - Renesas Technology Corp |
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377 / 1504 page ![]() Section 9 Bus Controller (BSC) Rev. 2.00 Sep. 24, 2008 Page 345 of 1468 REJ09B0412-0200 A refresh cycle is not executed during a consecutive cluster transfer even if a refresh request is generated. Therefore, user program must control the time so that each bank should not be activated over a given specification. The external bus is not released during a cluster transfer. T p T r T cb T c2 T cb T cb T cb T cb T c1 T cl PALL ACTV READ NOP Address bus Row Cloumn 1 Cloumn 2 Cloumn 3 Cloumn 4 Cloumn 5 Cloumn 6 SDRAM φ CS Precharge-sel RAS CAS WE CKE DQMUU DQMUL D31 to D24 D23 to D16 DQMLU DQMLL D7 to D0 BS RD/ WR D15 to D8 Row High Figure 9.91 Word-Size 6-Word Cluster Transfer (Read, BE = 1, EDDS = 1, CAS Latency = 2) |
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