H8SXSLASH1663R datasheet(411/1504 Pages) RENESAS

411 / 1504 page

Section 10 DMA Controller (DMAC)

Rev. 2.00 Sep. 24, 2008 Page 379 of 1468

REJ09B0412-0200

10.3

The DMAC has the following registers.

Channel 0:

• DMA source address register_0 (DSAR_0)

• DMA destination address register_0 (DDAR_0)

• DMA offset register_0 (DOFR_0)

• DMA transfer count register_0 (DTCR_0)

• DMA block size register_0 (DBSR_0)

• DMA mode control register_0 (DMDR_0)

• DMA address control register_0 (DACR_0)

• DMA module request select register_0 (DMRSR_0)

Channel 1:

• DMA source address register_1 (DSAR_1)

• DMA destination address register_1 (DDAR_1)

• DMA offset register_1 (DOFR_1)

• DMA transfer count register_1 (DTCR_1)

• DMA block size register_1 (DBSR_1)

• DMA mode control register_1 (DMDR_1)

• DMA address control register_1 (DACR_1)

• DMA module request select register_1 (DMRSR_1)

Channel 2:

• DMA source address register_2 (DSAR_2)

• DMA destination address register_2 (DDAR_2)

• DMA offset register_2 (DOFR_2)

• DMA transfer count register_2 (DTCR_2)

• DMA block size register_2 (DBSR_2)

• DMA mode control register_2 (DMDR_2)

• DMA address control register_2 (DACR_2)

• DMA module request select register_2 (DMRSR_2)

H8SX/1663R Datenblatt(PDF) 411 Page - Renesas Technology Corp