H8SXSLASH1663R datasheet(407/1504 Pages) RENESAS

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Section 10 DMA Controller (DMAC)

Rev. 2.00 Sep. 24, 2008 Page 375 of 1468

REJ09B0412-0200

Section 10 DMA Controller (DMAC)

This LSI includes a 4-channel DMA controller (DMAC).

10.1

Features

• Maximum of 4-G byte address space can be accessed

• Byte, word, or longword can be set as data transfer unit

• Maximum of 4-G bytes (4,294,967,295 bytes) can be set as total transfer size

Supports free-running mode in which total transfer size setting is not needed

• DMAC activation methods are auto-request, on-chip module interrupt, and external request.

Auto request:

CPU activates (cycle stealing or burst access can be selected)

On-chip module interrupt: Interrupt requests from on-chip peripheral modules can be selected

as an activation source

External request:

Low level or falling edge detection of the

DREQ signal can be

selected. External request is available for all four channels.

• Dual or single address mode can be selected as address mode

Dual address mode: Both source and destination are specified by addresses

Single address mode: Either source or destination is specified by the

DACK signal and the

other is specified by address

• Normal, repeat, or block transfer can be selected as transfer mode

Normal transfer mode:

One byte, one word, or one longword data is transferred at a

single transfer request

Repeat transfer mode:

One byte, one word, or one longword data is transferred at a

single transfer request

Repeat size of data is transferred and then a transfer address

returns to the transfer start address

Up to 64K transfers (65,536 bytes/words/longwords) can be set as

repeat size

Block transfer mode:

One block data is transferred at a single transfer request

Up to 64K transfers (65,536 bytes/words/longwords) can be set as

block size

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