H8SXSLASH1663R datasheet(408/1504 Pages) RENESAS

408 / 1504 page

Section 10 DMA Controller (DMAC)

Rev. 2.00 Sep. 24, 2008 Page 376 of 1468

REJ09B0412-0200

• Extended repeat area function which repeats the addressees within a specified area using the

transfer address with the fixed upper bits (ring buffer transfer can be performed, as an

example) is available

One bit (two bytes) to 27 bits (128 Mbytes) for transfer source and destination can be set as

extended repeat areas

• Address update can be selected from fixed address, offset addition, and increment or

decrement by 1, 2, or 4

Address update by offset addition enables to transfer data at addresses which are not placed

continuously

• Word or longword data can be transferred to an address which is not aligned with the

respective boundary

Data is divided according to its address (byte or word) when it is transferred

• Two types of interrupts can be requested to the CPU

A transfer end interrupt is generated after the number of data specified by the transfer counter

is transferred. A transfer escape end interrupt is generated when the remaining total transfer

size is less than the transfer data size at a single transfer request, when the repeat size of data

transfer is completed, or when the extended repeat area overflows.

• Module stop state can be set.

H8SX/1663R Datenblatt(PDF) 408 Page - Renesas Technology Corp