H8SXSLASH1663R datasheet(440/1504 Pages) RENESAS

440 / 1504 page

Section 10 DMA Controller (DMAC)

Rev. 2.00 Sep. 24, 2008 Page 408 of 1468

REJ09B0412-0200

Transfer

Address TA

Address TB

Address BB

Address BA

Operation when the repeat area is specified

to the source side

Repeat size =

BKSZH

data access size

Total transfer

size (DTCR)

Figure 10.9 Operations in Repeat Transfer Mode

(3)

Block Transfer Mode

In block transfer mode, one block size of data is transferred at a single transfer request. Up to 4

Gbytes can be specified as total transfer size by DTCR. The block size can be specified in DBSR

up to 64K

× data access size.

While one block of data is being transferred, transfer requests from other channels are suspended.

When the transfer is completed, the bus is released to the other bus master.

The block area can be specified for the source or destination address side by bits ARS1 and ARS0

in DACR. The address specified as the block area returns to the transfer start address when the

block size of data is completed. When the block area is specified as neither source nor destination

address side, the operation continues without returning the address to the transfer start address. A

repeat size end interrupt can be requested.

The

TEND signal is output every time 1-block data is transferred in the last DMA transfer cycle.

When an interrupt request by an extended repeat area overflow is used in block transfer mode,

settings should be selected carefully. For details, see section 10.5.5, Extended Repeat Area

Function.

H8SX/1663R Datenblatt(PDF) 440 Page - Renesas Technology Corp