H8SXSLASH1663R datasheet(438/1504 Pages) RENESAS

Teilenummer	H8SX/1663R

Bauteilbeschribung	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

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Section 10 DMA Controller (DMAC)

Rev. 2.00 Sep. 24, 2008 Page 406 of 1468

REJ09B0412-0200

10.5.2

Transfer Modes

(1)

Normal Transfer Mode

In normal transfer mode, one data access size of data is transferred at a single transfer request. Up

to 4 Gbytes can be specified as a total transfer size by DTCR. DBSR is ignored in normal transfer

mode.

The

TEND signal is output only in the last DMA transfer.

Figure 10.7 shows an example of the signal timing in normal transfer mode and figure 10.8 shows

the operation in normal transfer mode.

Read

Write

Read

Write

DMA transfer

cycle

Last DMA

transfer cycle

Bus cycle

Auto request transfer in dual address mode:

External request transfer in single address mode:

TEND

DMA

DREQ

Bus cycle

DACK

Figure 10.7 Example of Signal Timing in Normal Transfer Mode

Transfer

Total transfer

size (DTCR)

Address TA

Address BA

Address TB

Address BB

Figure 10.8 Operations in Normal Transfer Mode

H8SX/1663R Datenblatt(PDF) 438 Page - Renesas Technology Corp