H8SXSLASH1663R datasheet(439/1504 Pages) RENESAS

439 / 1504 page

Section 10 DMA Controller (DMAC)

Rev. 2.00 Sep. 24, 2008 Page 407 of 1468

REJ09B0412-0200

(2)

Repeat Transfer Mode

In repeat transfer mode, one data access size of data is transferred at a single transfer request. Up

to 4 Gbytes can be specified as a total transfer size by DTCR. The repeat size can be specified in

DBSR up to 65536

× data access size.

The repeat area can be specified for the source or destination address side by bits ARS1 and ARS0

in DACR. The address specified as the repeat area returns to the transfer start address when the

repeat size of transfers is completed. This operation is repeated until the total transfer size

specified in DTCR is completed. When H'00000000 is specified in DTCR, it is regarded as the

free running mode and repeat transfer is continued until the DTE bit in DMDR is cleared to 0.

In addition, a DMA transfer can be stopped and a repeat size end interrupt can be requested to the

CPU or DTC when the repeat size of transfers is completed. When the next transfer is requested

after completion of a 1-repeat size data transfer while the RPTIE bit is set to 1, the DTE bit in

DMDR is cleared to 0 and the ESIF bit in DMDR is set to 1 to complete the transfer. At this time,

an interrupt is requested to the CPU or DTC when the ESIE bit in DMDR is set to 1.

The timing of the

TEND signals is the same as in normal transfer mode.

Figure 10.9 shows the operation in repeat transfer mode while dual address mode is set.

When the repeat area is specified as neither source nor destination address side, the operation is

the same as the normal transfer mode operation shown in figure 10.8. In this case, a repeat size

end interrupt can also be requested to the CPU when the repeat size of transfers is completed.

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