H8SXSLASH1663R datasheet(480/1504 Pages) RENESAS

480 / 1504 page

Section 10 DMA Controller (DMAC)

Rev. 2.00 Sep. 24, 2008 Page 448 of 1468

REJ09B0412-0200

10.7.2

Bus Arbitration among DMAC and Other Bus Masters

When DMA transfer cycles are consecutively performed, bus cycles of other bus masters may be

inserted between the transfer cycles. The DMAC can release the bus temporarily to pass the bus to

other bus masters.

The consecutive DMA transfer cycles may not be divided according to the transfer mode settings

to achieve high-speed access.

The read and write cycles of a DMA transfer are not separated. Refreshing, external bus release,

and on-chip bus master (CPU, DTC, or EXDMAC) cycles are not inserted between the read and

write cycles of a DMA transfer.

In block transfer mode and an auto request transfer by burst access, bus cycles of the DMA

transfer are consecutively performed. For this duration, since the DMAC has priority over the

CPU and DTC, accesses to the external space is suspended (the IBCCS bit in the bus control

When the bus is passed to another channel or an auto request transfer by cycle stealing, bus cycles

of the DMAC and on-chip bus master are performed alternatively.

When the arbitration function among the DMAC and on-chip bus masters is enabled by setting the

IBCCS bit in BCR2, the bus is used alternatively except the bus cycles which are not separated.

For details, see section 9, Bus Controller (BSC).

A conflict may occur between external space access of the DMAC and a refreshing cycle,

EXDMAC cycle, or external bus release cycle. Even if a burst or block transfer is performed by

the DMAC, the transfer is stopped temporarily and a cycle of external bus release is inserted by

the BSC according to the external bus priority (when the CPU external access and the DTC

external access do not have priority over a DMAC transfer, the transfers are not operated until the

DMAC releases the bus).

In dual address mode, the DMAC releases the external bus after the external space write cycle.

Since the read and write cycles are not separated, the bus is not released.

An internal space (on-chip memory and internal I/O registers) access of the DMAC and refreshing

cycle, EXDMAC cycle, or an external bus release cycle may be performed at the same time.

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