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H8SX/1663R Datenblatt(PDF) 529 Page - Renesas Technology Corp

Teilenummer H8SX/1663R
Bauteilbeschribung  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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Hersteller  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663R Datenblatt(HTML) 529 Page - Renesas Technology Corp

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Section 11 EXDMA Controller (EXDMAC)
Rev. 2.00 Sep. 24, 2008 Page 497 of 1468
REJ09B0412-0200
In figure 11.18, the offset addition method is set for updating the transfer source address, and the
method of increment/decrement 1, 2 or 4 is set for updating the transfer destination address. For
updating the second and subsequent transfer source addresses, the data of the address for which
the offset value is added to the previous transfer address is read. This data is written to the
successive area on the transfer destination.
(2)
Example of XY conversion using offset
Figure 11.19 shows the XY conversion by combining the repeat transfer mode and offset
addition.
Data 1
Data 2
Data 3
Data 4
Data 5
Data 11
Data 12
Data 16
Data 16
Data 15
Data 14
Data 13
Data 10
Data 9
Data 8
Data 7
Data 6
Data 1
Data 5
Data 9
Data 13
Data 2
Data 11
Data 15
Data 12
Data 8
Data 4
Data 7
Data 3
Data 14
Data 10
Data 6
First cycle
1st transfer
Second cycle
2nd transfer
Third cycle
3rd transfer
First cycle
First cycle
Second cycle
Third cycle
Fourth cycle
Data 1
Data 2
Data 3
Data 4
Data 15
Data 5
Data 11
Data 12
Data 16
Data 14
Data 13
Data 10
Data 9
Data 8
Data 7
Data 6
Data 1
Data 2
Data 3
Data 4
Data 15
Data 5
Data 11
Data 12
Data 16
Data 14
Data 13
Data 10
Data 9
Data 8
Data 7
Data 6
Data 1
Data 2
Data 3
Data 4
Data 15
Data 5
Data 11
Data 12
Data 16
Data 14
Data 13
Data 10
Data 9
Data 8
Data 7
Data 6
Data 1
Data 5
Data 9
Data 13
Data 12
Data 2
Data 11
Data 15
Data 16
Data 8
Data 4
Data 7
Data 3
Data 14
Data 10
Data 6
Transfer
Transfer
Interrupt
requested
Interrupt
requested
Address
restored
Interrupt
requested
Address
restored
Transfer source
address
overwritten
by CPU
Transfer source
address
overwritten
by CPU
Offset value
Offset value
Offset value
Figure 11.19 XY Conversion by Combining Repeat Transfer Mode and Offset Addition
In figure 11.19, the source address side is set as a repeat area in EDACR and the offset addition is
set in EDACR. The offset value is the address that corresponds to 4
× data access size (example:
for a longword-size transfer, H'00000010 is specified in EDOFR). The repeat size is 4
× data
access size (example: for a longword-size transfer, 4
× 4 = 16 bytes are specified as a repeat size).
The increment by 1, 2 or 4 is set for the transfer destination. The RPTIE bit in EDACR is set to 1
to generate a repeat size end interrupt request at the end of a repeat-size transfer.



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