H8SXSLASH1663R datasheet(530/1504 Pages) RENESAS

530 / 1504 page

Section 11 EXDMA Controller (EXDMAC)

Rev. 2.00 Sep. 24, 2008 Page 498 of 1468

REJ09B0412-0200

When transfer starts, the offset value is added to the transfer source address and the data is

transferred. The data is aligned in the order of transfer in the transfer destination. After up to data

4 is transferred, the EXDMAC assumes that a repeat-size transfer completed, and restores the

transfer source address to the transfer start address (address of transfer source data 1). At the same

time, a repeat size end interrupt is requested. This interrupt request aborts the transfer temporarily.

Overwrite the EDSAR value to the data 5 address by accessing the I/O register via the CPU. (For

longword transfer, add 4 to the address of data 1.) When the DTE bit in EDMDR is set to 1,

transfer is resumed from the state in which the transfer is aborted. The transfer source data is XY-

converted and transferred to the transfer destination by repeating the above processing.

Figure 11.20 shows the XY conversion flow.

: User side

:EXDMAC side

Start

Set address and transfer count

Set repeat transfer mode

Set DTE bit to 1

Transfer request accepted

Data transfer

Transfer counter and

repeat size decremented

Enable repeat cancel interrupt

Set transfer source address + 4

Transfer source address restored

End of repeat size

Interrupt requested

Transfer count = 0

Repeat size = 0

End

Yes

(For longword transfer)

Figure 11.20 Flow of XY Conversion Combining Repeat Transfer Mode and Offset

Addition

H8SX/1663R Datenblatt(PDF) 530 Page - Renesas Technology Corp