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H8SX/1663R Datenblatt(PDF) 532 Page - Renesas Technology Corp

Teilenummer H8SX/1663R
Bauteilbeschribung  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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Hersteller  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
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H8SX/1663R Datenblatt(HTML) 532 Page - Renesas Technology Corp

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Section 11 EXDMA Controller (EXDMAC)
Rev. 2.00 Sep. 24, 2008 Page 500 of 1468
REJ09B0412-0200
When a block area (repeat area) is set for the source address in block transfer mode (or repeat
transfer mode), the source address is restored to the transfer start address at the end of block-size
(repeat-size) transfer and is not affected by address updating.
When an extended repeat area is set for the source address, the operation conforms to that setting.
The upper addresses set for the extended repeat area is fixed, and is not affected by address
updating.
When EDSAR is read during a transfer operation, a longword access must be used. During a
transfer operation, EDSAR may be updated without regard to accesses from the CPU, and the
correct values may not be read if the upper and lower words are read separately. Do not write to
EDSAR for a channel on which a transfer operation is in progress.
(2)
EXDMA Destination Address Register (EDDAR)
When the EDDAR address is accessed as the transfer destination, the EDDAR value is output, and
then EDDAR is updated with the address to be accessed next.
Bits DAT1 and DAT0 in EDACR specify incrementing or decrementing. The address is fixed
when DAT1 and DAT0 = B
′00, incremented by offset register value when DAT1 and DAT0 =
B
′01, incremented when DAT1 and DAT0 = B′10, and decremented when DAT1 and DAT0 =
B
′11. (The increment or decrement value is determined by the data access size.)
The DTSZ1 and DTSZ0 bits in EDMDR set the data access size. When DTSZ1 and DTSZ0 =
B
′00, the data is byte-size and the address is incremented or decremented by 1. When DTSZ1 and
DTSZ0 = B
′01, the data is word-size and the address is incremented or decremented by 2. When
DTSZ1 and DTSZ0 = B
′10, the data is longword-size and the address is incremented or
decremented by 4. When a word-size or longword-size is specified but the destination address is
not at the word or longword boundary, the data is divided into bytes or words for writing. When a
word or a longword is divided for writing, the address is incremented or decremented by 1 or 2
according to an actual byte- or word-size written. After a word-size or longword-size write, the
address is incremented or decremented to or from the write start address according to the setting of
SAT1 and SAT0.
When a block area (repeat area) is set for the destination address in block transfer mode (or repeat
transfer mode), the destination address is restored to the transfer start address at the end of block-
size (repeat-size) transfer and is not affected by address updating.
When an extended repeat area is set for the destination address, the operation conforms to that
setting. The upper addresses set for the extended repeat area is fixed, and is not affected by
address updating.



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