H8SXSLASH1663R datasheet(542/1504 Pages) RENESAS

542 / 1504 page

Section 11 EXDMA Controller (EXDMAC)

Rev. 2.00 Sep. 24, 2008 Page 510 of 1468

REJ09B0412-0200

(4)

EDREQ Pin Falling Edge Activation Timing

Figure 11.29 shows an example of normal transfer mode transfer activated by the

EDREQ pin

falling edge.

EDREQ pin sampling is performed in each cycle starting at the next rise of Bφ after the end of the

DTE bit write cycle.

When a low level is sampled at the

EDREQ pin while acceptance of a transfer request via the

EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated

within the EXDMAC, the request is cleared, and

EDREQ pin high level sampling for edge sensing

is started. If

EDREQ pin high level sampling is completed by the end of the EXDMA write cycle,

acceptance resumes after the end of the write cycle, and

EDREQ pin low level sampling is

performed again. This sequence of operations is repeated until the end of the transfer.

Request

Request clearance period

Minimum 3 cycles

Transfer

source

Transfer

destination

Transfer

destination

Transfer

source

Bus release

EXDMA read

EXDMA write

EXDMA read EXDMA write

EDREQ

Address bus

EXDMA

control

Channel

[1]

[2]

[3]

[4]

[5]

[6]

[7]

Acceptance resumed

[1] Acceptance after transfer enabling;

EDREQ pin low level is sampled at rise of Bφ, and request is held.

[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.

[3], [6] EXDMA cycle starts;

EDREQ pin high level sampling is started at rise of Bφ.

[4], [7] When

EDREQ pin high level has been sampled, acceptance is resumed after completion of write cycle.

(As in [1],

EDREQ pin low level is sampled at rise of Bφ, and request is held.)

Idle

Read

Write

Read

Write

Figure 11.29 Example of Normal Transfer Mode Transfer Activated

EDREQ Pin Falling Edge

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