H8SXSLASH1663R datasheet(546/1504 Pages) RENESAS

546 / 1504 page

Section 11 EXDMA Controller (EXDMAC)

Rev. 2.00 Sep. 24, 2008 Page 514 of 1468

REJ09B0412-0200

(6)

EDREQ Pin Low Level Activation Timing with NRD = 1 Specified

When the NRD bit is set to 1 in EDMDR, the acceptance timing of the next transfer request can be

delayed one cycle later.

Figure 11.33 shows an example of normal transfer mode transfer activated by the

EDREQ pin low

level with NRD = 1 specified.

EDREQ pin sampling is performed in each cycle starting at the next rise of Bφ after the end of the

DTE bit write cycle.

When a low level is sampled at the

EDREQ pin while acceptance of a transfer request via the

EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated

within the EXDMAC, the request is cleared. After the end of the write cycle, acceptance resumes

when one cycle of the request clearance period specified by NRD = 1 expires and

EDREQ pin low

level sampling is performed again. This sequence of operations is repeated until the end of the

transfer.

Request clearance period

Transfer

source

Transfer

destination

Transfer

destination

Transfer

source

Bus release

EXDMA read EXDMA write

EDREQ

Address

bus

Channel

[1]

[2]

[3]

[4]

[5]

[6]

[7]

Acceptance resumed

[1] Acceptance after transfer enabling;

EDREQ pin low level is sampled at rise of Bφ, and request is held.

[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.

[3], [6] EXDMA cycle starts.

[4], [7] Acceptance is resumed after completion of write cycle plus one cycle.

(As in [1],

EDREQ pin low level is sampled at rise of Bφ, and request is held.)

Request

Minimum 3 cycles

Request clearance period

Extended request

clearance period

specified by NRD

Extended request

clearance period

specified by NRD

Figure 11.33 Example of Normal Transfer Mode Transfer Activated

EDREQ Pin Low Level with NRD = 1 Specified

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