H8SXSLASH1663R datasheet(552/1504 Pages) RENESAS

552 / 1504 page

Section 11 EXDMA Controller (EXDMAC)

Rev. 2.00 Sep. 24, 2008 Page 520 of 1468

REJ09B0412-0200

11.5.12

Operation Timing in Each Mode

This section describes examples of operation timing in each mode. The CPU external bus cycle is

shown as an example of conflict with another bus master.

(1)

Auto-Request/Normal Transfer Mode/Cycle Steal Mode

With auto-request (in cycle steal mode), when the DTE bit is set to 1 in EDMDR, an EXDMA

transfer cycle is started a minimum of three cycles later. If there is a transfer request for another

channel of higher priority, the transfer request by the original channel is held pending, and transfer

is performed on the higher-priority channel from the next transfer. Transfer on the original channel

is resumed on completion of the higher-priority channel transfer.

Figures 11.39 and 11.40 show operation timing examples for various conditions.

3 cycles

Bus release

EXDMA

write

EXDMA

read

EXDMA

write

EXDMA

read

Bus cycle

CPU operation

ETEND

DTE bit

3 cycles

EXDMA

write

EXDMA

read

Bus

release

Bus

release

Bus

release

DTE 1

write

Internal bus space cycles

3 cycles

Last transfer cycle

Figure 11.39 Auto-Request/Normal Transfer Mode/Cycle Steal Mode

(No Conflict/Dual Address Mode)

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