H8SXSLASH1663R datasheet(550/1504 Pages) RENESAS

550 / 1504 page

Section 11 EXDMA Controller (EXDMAC)

Rev. 2.00 Sep. 24, 2008 Page 518 of 1468

REJ09B0412-0200

(4)

EDREQ Pin Low Level Activation Timing

Figure 11.37 shows an example of single address mode transfer activated by the

EDREQ pin low

level.

EDREQ pin sampling is performed in each cycle starting at the next rise of Bφ after the end of the

DTE bit write cycle.

When a low level is sampled at the

EDREQ pin while acceptance of a transfer request via the

EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated

within the EXDMAC, the request is cleared. After the end of the single cycle, acceptance resumes

and

EDREQ pin low level sampling is performed again. This sequence of operations is repeated

until the end of the transfer.

Request

Idle

Request

Minimum 3 cycles

Transfer source/

Transfer destination

Single

Bus

release

Bus

release

Bus

release

EXDMA single

EDREQ

Address bus

EXDMA control

Channel

[1]

[2]

[3]

[4]

[5]

[6]

[7]

Acceptance resumed

[1] Acceptance after transfer enabling;

EDREQ pin low level is sampled at rise of Bφ, and request is held.

[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.

[3], [6] EXDMA cycle starts.

[4], [7] Acceptance is resumed after completion of single cycle.

(As in [1],

EDREQ pin low level is sampled at rise of Bφ, and request is held.)

Transfer source/

Transfer destination

Single

EDACK

Request clearance period

Figure 11.37 Example of Single Address Mode Transfer Activated

EDREQ Pin Low Level

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