H8SXSLASH1663R datasheet(565/1504 Pages) RENESAS

565 / 1504 page

Section 11 EXDMA Controller (EXDMAC)

Rev. 2.00 Sep. 24, 2008 Page 533 of 1468

REJ09B0412-0200

The cluster size is decremented regardless of the read or write operation in the consecutive write

sequences.

Cluster buffer

Transfer source memory

Transfer destination memory

MSB

H'AA0000

Long Word

Word

Byte

H'AA0004

H'AA0008

H'AA000C

H'AA0010

LSB

H'BB0000

Long Word

Word

H'BB0004

H'BB0008

H'BB000C

H'BB0010

CLSBR0

CLSBR1

CLSBR2

CLSBR3

CLSBR4

CLSBR5

CLSBR6

CLSBR7

Figure 11.56 Odd Address Transfer

(2)

Cluster Transfer Read Address Mode (AMS = 1, DIRS = 0)

In this mode, the transfer source address is specified in the source address register (EDSAR) and

data is read from the transfer source and transferred to the cluster buffer. In this mode, the TSEIE

bit in the mode control register (EDMDR) must be set to 1.

Two data access size to 32 bytes can be specified as a cluster size for the consecutive read

operation.

The cycles in a cluster-size transfer are indivisible: another bus cycle (external access by another

bus master, refresh cycle, or external bus release cycle) does not occur in a cluster-size transfer.

ETEND pin output can be enabled or disabled by means of the ETENDE bit in EDMDR. ETEND

is output for the last read cycle. When an idle cycle is inserted before the last read cycle, the

ETEND signal is also output in the idle cycle.

In this mode, the EDACKE bit in EDMDR must be set to 0 to disable the

EDACK pin output.

Figure 11.57 shows the data flow in the cluster transfer read address mode (from the external

memory to the cluster buffer), and figure 11.58 shows an example of the timing in cluster transfer

read address mode.

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