H8SXSLASH1663R datasheet(567/1504 Pages) RENESAS

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Section 11 EXDMA Controller (EXDMAC)

Rev. 2.00 Sep. 24, 2008 Page 535 of 1468

REJ09B0412-0200

(3)

Cluster Transfer Write Address Mode (AMS = 1, DIRS = 1)

In this mode, the transfer destination address is specified in the destination address register

(EDDAR) and data in the cluster butter is written to the transfer destination. In this mode, the

TSEIE bit in the mode control register (EDMDR) must be set to 1.

One data access size to 32 bytes can be specified as a cluster size for the consecutive write

operation. When one data access size is specified as a cluster size, the cluster transfer write

address mode is used.

The cycles in a cluster-size transfer are indivisible: another bus cycle (external access by another

bus master, refresh cycle, or external bus release cycle) does not occur in a cluster-size transfer.

ETEND pin output can be enabled or disabled by means of the ETENDE bit in EDMDR. ETEND

is output for the last write cycle. When an idle cycle is inserted before the last write cycle, the

ETEND signal is also output in the idle cycle.

In this mode, the EDACKE bit in EDMCR must be set to 0 to disable the

EDACK pin output.

Figure 11.59 shows the data flow in the cluster transfer write address mode (from the cluster

buffer to the external memory), and figure 11.60 shows an example of the timing in cluster

transfer write address mode.

LSI

Transfer

destination

external

memory

EDDAR access

External data bus

Cluster buffer

When initializing an area by the specified data, write the specified data from cluster buffer 0 into a register

sequentially. Then, specify the buffer size written in the register as a cluster size and the area to be initialized

as DAR, and then execute transfer in this mode.

Figure 11.59 Data Flow in Cluster Transfer Write Address Mode

(from Cluster Buffer to External Memory)

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