H8SXSLASH1663R datasheet(591/1504 Pages) RENESAS

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Section 12 Data Transfer Controller (DTC)

Rev. 2.00 Sep. 24, 2008 Page 559 of 1468

REJ09B0412-0200

Section 12 Data Transfer Controller (DTC)

This LSI includes a data transfer controller (DTC). The DTC can be activated to transfer data by

an interrupt request.

12.1

Features

• Transfer possible over any number of channels:

Multiple data transfer enabled for one activation source (chain transfer)

Chain transfer specifiable after data transfer (when the counter is 0)

• Three transfer modes

Normal/repeat/block transfer modes selectable

Transfer source and destination addresses can be selected from increment/decrement/fixed

• Short address mode or full address mode selectable

 Short address mode

Transfer information is located on a 3-longword boundary

The transfer source and destination addresses can be specified by 24 bits to select a 16-

Mbyte address space directly

 Full address mode

Transfer information is located on a 4-longword boundary

The transfer source and destination addresses can be specified by 32 bits to select a 4-

Gbyte address space directly

• Size of data for data transfer can be specified as byte, word, or longword

The bus cycle is divided if an odd address is specified for a word or longword transfer.

The bus cycle is divided if address 4n + 2 is specified for a longword transfer.

• A CPU interrupt can be requested for the interrupt that activated the DTC

A CPU interrupt can be requested after one data transfer completion

A CPU interrupt can be requested after the specified data transfer completion

• Read skip of the transfer information specifiable

• Writeback skip executed for the fixed transfer source and destination addresses

• Module stop state specifiable

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