H8SXSLASH1663R datasheet(588/1504 Pages) RENESAS

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Section 11 EXDMA Controller (EXDMAC)

Rev. 2.00 Sep. 24, 2008 Page 556 of 1468

REJ09B0412-0200

11.10

Usage Notes

1. EXDMAC Register Access during Operation

Except for clearing the DTE bit to 0 in EDMDR, settings should not be changed for a channel

in operation (including the transfer standby state). Transfer must be disabled before changing a

setting for an operational channel.

2. Module Stop State

The EXDMAC operation can be enabled or disabled by the module stop control register. The

initial value is "enabled".

When the MSTPA14 bit is set to 1 in MSTPCRA, the EXDMAC clock stops and the

EXDMAC enters the module stop state. However, 1 cannot be written to the MSTPA14 bit

when any of the EXDMAC's channels is enabled for transfer, or when an interrupt is being

requested. Before setting the MSTPA14 bit, first clear the DTE bit in EDMDR to 0, then clear

the DTIF or DTIE bit in EDMDR to 0.

When the EXDMAC clock stops, EXDMAC registers can no longer be accessed. The

following EXDMAC register settings remain valid in the module stop state, and so should be

disabled, if necessary, before making the module stop transition.

• ETENDE = 1 in EDMDR (ETEND pin enable)

• EDRAKE = 1 in EDMDR (EDRAK pin enable)

• EDACKE = 1 in EDMDR (EDACK pin enable)

EDREQ Pin Falling Edge Activation

Falling edge sensing on the

EDREQ pin is performed in synchronization with EXDMAC

internal operations, as indicated below.

1. Activation request standby state: Waits for low level sensing on

EDREQ pin, then goes to

[2].

2. Transfer standby state: Waits for EXDMAC data transfer to become possible, then goes to

[3].

3. Activation request disabled state: Waits for high level sensing on

EDREQ pin, then goes to

[1].

After EXDMAC transfer is enabled, the EXDMAC goes to state [1], so low level sensing is

used for the initial activation after transfer is enabled.

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