H8SXSLASH1663R datasheet(620/1504 Pages) RENESAS

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Section 12 Data Transfer Controller (DTC)

Rev. 2.00 Sep. 24, 2008 Page 588 of 1468

REJ09B0412-0200

12.6

DTC Activation by Interrupt

The procedure for using the DTC with interrupt activation is shown in figure 12.15.

Clearing the RRS bit in DTCCR to 0 clears the read skip flag

of transfer information. Read skip is not performed when the

DTC is activated after clearing the RRS bit. When updating

transfer information, the RRS bit must be cleared.

Set the MRA, MRB, SAR, DAR, CRA, and CRB transfer

information in the data area. For details on setting transfer

information, see section 12.2, Register Descriptions. For details

on location of transfer information, see section 12.4, Location of

Transfer Information and DTC Vector Table.

Set the start address of the transfer information in the DTC

vector table. For details on setting DTC vector table, see section

12.4, Location of Transfer Information and DTC Vector Table.

Setting the RRS bit to 1 performs a read skip of second time or

later transfer information when the DTC is activated consecu-

tively by the same interrupt source. Setting the RRS bit to 1 is

always allowed. However, the value set during transfer will be

valid from the next transfer.

Set the bit in DTCER corresponding to the DTC activation

interrupt source to 1. For the correspondence of interrupts and

DTCER, refer to table 12.1. The bit in DTCER may be set to 1 on

the second or later transfer. In this case, setting the bit is not

needed.

Set the enable bits for the interrupt sources to be used as the

activation sources to 1. The DTC is activated when an interrupt

used as an activation source is generated. For details on the

settings of the interrupt enable bits, see the corresponding

descriptions of the corresponding module.

After the end of one data transfer, the DTC clears the activation

source flag or clears the corresponding bit in DTCER and

requests an interrupt to the CPU. The operation after transfer

depends on the transfer information. For details, see section

12.2, Register Descriptions and figure 12.4.

DTC activation by interrupt

Clear RRS bit in DTCCR to 0

Set transfer information

(MRA, MRB, SAR, DAR,

CRA, CRB)

Set starts address of transfer

information in DTC vector table

Set RRS bit in DTCCR to 1

Set corresponding bit in

DTCER to 1

Set enable bit of interrupt

request for activation source

to 1

Interrupt request generated

DTC activated

Corresponding bit in DTCER

cleared or CPU interrupt

requested

Transfer end

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[1]

[2]

[3]

[4]

[5]

[6]

[7]

Determine

clearing method of

activation source

Clear

activation

source

Clear corresponding

bit in DTCER

Figure 12.15 DTC with Interrupt Activation

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