H8SXSLASH1663R datasheet(618/1504 Pages) RENESAS

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Section 12 Data Transfer Controller (DTC)

Rev. 2.00 Sep. 24, 2008 Page 586 of 1468

REJ09B0412-0200

12.5.9

Number of DTC Execution Cycles

Table 12.9 shows the execution status for a single DTC data transfer, and table 12.10 shows the

number of cycles required for each execution.

Table 12.9

DTC Execution Status

Mode

Vector

Read

Transfer

Information

Read

Transfer

Information

Write

Data Read

Data Write

Internal

Operation

Normal 1

2.3

Repeat 1

2.3

Block

transfer

2.3

3•P*

2•P*

1•P 3•P*

2•P*

1•P

[Legend]

P: Block size (CRAH and CRAL value)

Note:

1. When transfer information read is skipped

2. In full address mode operation

3. In short address mode operation

4. When the SAR or DAR is in fixed mode

5. When the SAR and DAR are in fixed mode

6. When a longword is transferred while an odd address is specified in the address

7. When a word is transferred while an odd address is specified in the address register or

when a longword is transferred while address 4n + 2 is specified

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