H8SXSLASH1663R datasheet(636/1504 Pages) RENESAS

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Section 13 I/O Ports

Rev. 2.00 Sep. 24, 2008 Page 604 of 1468

REJ09B0412-0200

13.1.1

Data Direction Register (PnDDR) (n = 1, 2, 3, 6, A to F, H to K, and M)

DDR is an 8-bit write-only register that specifies the port input or output for each bit. A read from

the DDR is invalid and DDR is always read as an undefined value.

When the general I/O port function is selected, the corresponding pin functions as an output port

by setting the corresponding DDR bit to 1; the corresponding pin functions as an input port by

clearing the corresponding DDR bit to 0.

The initial DDR values are shown in table 13.3.

Bit

Bit Name

Initial Value

R/W

Notes: The lower six bits are valid and the upper two bits are reserved for port 6 registers.

The lower five bits are valid and the upper three bits are reserved for port M registers.

Bits 2 and 3 are valid and the other bits are reserved for port C registers.

Registers of ports J and K cannot be accessed when PCJKE = 0.

Registers of ports D and E cannot be accessed when PCJKE = 1.

Pn7DDR

Pn6DDR

Pn5DDR

Pn4DDR

Pn3DDR

Pn2DDR

Pn1DDR

Pn0DDR

Table 13.3

Startup Mode and Initial Value

Startup Mode

Port

External Extended Mode

Single-Chip Mode

Port A

H'80

H'00

Other ports

H'00

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