H8SXSLASH1663R datasheet(638/1504 Pages) RENESAS

638 / 1504 page

Section 13 I/O Ports

Rev. 2.00 Sep. 24, 2008 Page 606 of 1468

REJ09B0412-0200

13.1.4

Input Buffer Control Register (PnICR) (n = 1, 2, 3, 5, 6, A to F, H to K, and M)

ICR is an 8-bit readable/writable register that controls the port input buffers.

For bits in ICR set to 1, the input buffers of the corresponding pins are valid. For bits in ICR

cleared to 0, the input buffers of the corresponding pins are invalid and the input signals are fixed

high.

When the pin functions as an input for the peripheral modules, the corresponding bits should be

set to 1. The initial value should be written to a bit whose corresponding pin is not used as an input

or is used as an analog input/output pin.

When PORT is read, the pin state is always read regardless of the ICR value. When the ICR value

is cleared to 0 at this time, the read pin state is not reflected in a corresponding on-chip peripheral

module.

If ICR is modified, an internal edge may occur depending on the pin state. Accordingly, ICR

should be modified when the corresponding input pins are not used. For example, an

IRQ input,

modify ICR while the corresponding interrupt is disabled, clear the IRQF flag in ISR of the

interrupt controller to 0, and then enable the corresponding interrupt. If an edge occurs after the

ICR setting, the edge should be cancelled.

The initial value of ICR is H'00.

Notes: The lower six bits are valid and the upper two bits are reserved for port 6 registers.

The lower five bits are valid and the upper three bits are reserved for port M registers.

Bits 2 and 3 are valid and the other bits are reserved for port C registers.

Registers of ports J and K cannot be accessed when PCJKE = 0.

Registers of ports D and E cannot be accessed when PCJKE = 1.

Bit

Bit Name

Initial Value

R/W

Pn7ICR

R/W

Pn6ICR

R/W

Pn5ICR

R/W

Pn4ICR

R/W

Pn3ICR

R/W

Pn2ICR

R/W

Pn1ICR

R/W

Pn0ICR

R/W

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