H8SXSLASH1663R datasheet(637/1504 Pages) RENESAS

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Section 13 I/O Ports

Rev. 2.00 Sep. 24, 2008 Page 605 of 1468

REJ09B0412-0200

13.1.2

Data Register (PnDR) (n = 1, 2, 3, 6, A to F, H to K, and M)

DR is an 8-bit readable/writable register that stores the output data of the pins to be used as the

general output port.

The initial value of DR is H'00.

Notes: The lower six bits are valid and the upper two bits are reserved for port 6 registers.

The lower five bits are valid and the upper three bits are reserved for port M registers.

Bits 2 and 3 are valid and the other bits are reserved for port C registers.

Registers of ports J and K cannot be accessed when PCJKE = 0.

Registers of ports D and E cannot be accessed when PCJKE =1.

Bit

Bit Name

Initial Value

R/W

Pn7DR

R/W

Pn6DR

R/W

Pn5DR

R/W

Pn4DR

R/W

Pn3DR

R/W

Pn2DR

R/W

Pn1DR

R/W

Pn0DR

R/W

13.1.3

Port Register (PORTn) (n = 1, 2, 3, 5, 6, A to F, H to K, and M)

PORT is an 8-bit read-only register that reflects the port pin state. A write to PORT is invalid.

When PORT is read, the DR bits that correspond to the respective DDR bits set to 1 are read and

the status of each pin whose corresponding DDR bit is cleared to 0 is also read regardless of the

ICR value.

The initial value of PORT is undefined and is determined based on the port pin state.

Notes: The lower six bits are valid and the upper two bits are reserved for port 6 registers.

The lower five bits are valid and the upper three bits are reserved for port M registers.

Bits 2 and 3 are valid and the other bits are reserved for port C registers.

Registers of ports J and K cannot be accessed when PCJKE = 0.

Registers of ports D and E cannot be accessed when PCJKE = 1.

Bit

Bit Name

Initial Value

R/W

Pn7

Undefined

Pn6

Undefined

Pn5

Undefined

Pn4

Undefined

Pn3

Undefined

Pn2

Undefined

Pn1

Undefined

Pn0

Undefined

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