H8SXSLASH1663R datasheet(685/1504 Pages) RENESAS

685 / 1504 page

Section 13 I/O Ports

Rev. 2.00 Sep. 24, 2008 Page 653 of 1468

REJ09B0412-0200

Table 13.5

Available Output Signals and Settings in Each Port

Port

Output

Specification

Signal Name

Output

Signal

Name

Signal Selection Register

Settings

Peripheral Module Settings

EDRAK1_OE

EDRAK1

PFCR8.EDMAS1[A,B] =

SYSCR.EXPE = 1,

EDMDR_1.EDRAKE = 1

SCL0_OE

SCL0

ICCRA.ICE = 1

EDACK1A_OE EDACK1

PFCR8.EDMAS1[A,B] =

SYSCR.EXPE = 1, EDACR_1.AMS = 1,

EDMDR_1.EDACKE = 1

DACK1A_OE

DACK1

PFCR7.DMAS1[A,B] = 00

DMAC.DACR_1.AMS = 1,

DMDR_1.DACKE = 1

SDA0_OE

SDA0

ICCRA.ICE = 1

ETEND1A_OE ETEND1

PFCR8.EDMAS1[A,B] =

SYSCR.EXPE = 1,

EDMDR_1.ETENDE = 1

TEND1A_OE

TEND1

PFCR7.DMAS1[A,B] = 00

DMDR_1.TENDE = 1

SCL1_OE

SCL1

ICCRA.ICE = 1

TxD5_OE

TxD5

SCR.TE = 1, IrCR.IrE = 0

IrTxD_OE

IrTxD

SCR.TE = 1, IrCR.IrE = 1

SDA1_OE

SDA1

ICCRA.ICE = 1

EDRAK0_OE

EDRAK0

PFCR8.EDMAS0[A,B] =

SYSCR.EXPE = 1,

EDMDR_0.EDRAKE = 1

EDACK0A_OE EDACK0

PFCR8.EDMAS0[A,B] =

SYSCR.EXPE = 1, EDACR_0.AMS = 1,

EDMDR_0.EDACKE = 1

DACK0A_OE

DACK0

PFCR7.DMAS0[A,B] = 00

DMAC.DACR_0.AMS = 1,

DMDR_0.DACKE = 1

SCK2_OE

SCK2

When SCMR.SMIF = 1:

SCR.TE = 1 or SCR.RE = 1 while

SMR.GM = 0, SCR.CKE [1, 0] = 01 or

while SMR.GM = 1

When SCMR.SMIF = 0:

SCR.TE = 1 or SCR.RE = 1 while

SMR.C/A = 0, SCR.CKE [1, 0] = 01 or

while SMR.C/A = 1, SCR.CKE 1 = 0

ETEND0A_OE ETEND0

PFCR8.EDMAS0[A,B] =

SYSCR.EXPE = 1,

EDMDR_0.ETENDE = 1

TEND0A_OE

TEND0

PFCR7.DMAS0[A,B] = 00

DMDR_0.TENDE = 1

TxD2_OE

TxD2

SCR.TE = 1

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