H8SXSLASH1663R datasheet(758/1504 Pages) RENESAS

758 / 1504 page

Section 14 16-Bit Timer Pulse Unit (TPU)

Rev. 2.00 Sep. 24, 2008 Page 726 of 1468

REJ09B0412-0200

Bit

Bit Name

Initial

value

R/W

Description

TGFB

R/(W)* Input Capture/Output Compare Flag B

Status flag that indicates the occurrence of TGRB input

capture or compare match.

[Setting conditions]

• When TCNT = TGRB while TGRB is functioning as

output compare register

• When TCNT value is transferred to TGRB by input

capture signal while TGRB is functioning as input

capture register

[Clearing conditions]

• When DTC is activated by a TGIB interrupt while the

DISEL bit in MRB of DTC is 0

• When 0 is written to TGFB after reading TGFB = 1

(When the CPU is used to clear this flag by writing 0

while the corresponding interrupt is enabled, be sure

to read the flag after writing 0 to it.)

TGFA

R/(W)* Input Capture/Output Compare Flag A

Status flag that indicates the occurrence of TGRA input

capture or compare match.

[Setting conditions]

• When TCNT = TGRA while TGRA is functioning as

output compare register

• When TCNT value is transferred to TGRA by input

capture signal while TGRA is functioning as input

capture register

[Clearing conditions]

• When DTC is activated by a TGIA interrupt while the

DISEL bit in MRB of DTC is 0

• When DMAC is activated by a TGIA interrupt while

the DTA bit in DMDR of DMAC is 1

• When 0 is written to TGFA after reading TGFA = 1

(When the CPU is used to clear this flag by writing 0

while the corresponding interrupt is enabled, be sure

to read the flag after writing 0 to it.)

Note:

Only 0 can be written to clear the flag.

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